`timescale 1ns/1ns

module flow_led_FSM_tb();

reg Clk;
reg Rst_n;
wire [3:0]led;

initial
    begin
        Clk=1'b1;
        Rst_n<=1'b0;
        #20
        Rst_n<=1'b1;
    end

always #10 Clk<=~Clk;


water_led 
#(
    .CNT_MAX(25'd24)
)
water_led_inst
(
    .Clk(Clk),
    .Rst_n(Rst_n),

    .led(led)
);

endmodule	
                                   